UVM EXPRESS IS A SIMPLIFIED METHOD OF IMPLEMENTATION UVM

Author(s): Selivanov Ivan Vitalievich, Shubin Nikolay Yurievich

Rubric: Information technology

Release: 2014-2 (5)

Pages: 124-128

Keywords: SystemVerilog, universal verification methodology (UVM), testbench, functional coverage.

Annotation: UVM is an innovative methodology of functional verification allowing to standardize, simplify and speed up the verification process. However its full implementing takes a significant amount of time. This is what prevents its wider use. This article describes a step-by-step methodology of implementing the UVM which produces value since the first step.

Bibliography: Selivanov IV.VI., Shubin NI.YU. UVM EXPRESS IS A SIMPLIFIED METHOD OF IMPLEMENTATION UVM // Education Resources and Technologies. – 2014. – № 2 (5). – С. 124-128. doi: