# POWER ESTIMATION TECHNIQUES IN CMOS CIRCUIT DESIGN

**Author(s):**
Cheremisinova L.D.

**Rubric:**
Information technology

**DOI: **
10.21777/2500-2112-2018-4-50-59

**Release:**
2018-4 (25)

**Pages:**
50-59

**Keywords:**
VLSI design, power consumption, CMOS technology, simulation, power estimation

**Annotation:**
The design of low-power circuits is becoming increasingly important due to the fact that excessive energy dissipation by digital devices becomes an obstacle to further increase the integration level and VLSI complexity, as well as due to the expansion of the market of portable self-powered devices. The energy consumption depends on many electrical and topological parameters of the circuit, and its reduction can be ensured at different design levels. In this connection, one of the most important problems is the development of methods and tools for energy consumption estimation not only of circuits at the transistor level, but also for calculating forecast estimates in the process of their design. The paper deals with the problem of energy consumption estimation of microcircuits based on CMOS technology. The energy consumption estimate is understood as the estimate of the average value of the energy dissipated by the circuit. The paper presents an analytical survey of known methods for estimating the average energy consumption of static CMOS circuits in the normal mode of their operation, used at different design stages.

**Bibliography:**
Cheremisinova L.D. POWER ESTIMATION TECHNIQUES IN CMOS CIRCUIT DESIGN // Education Resources and Technologies. – 2018. – № 4 (25). – С. 50-59. doi: 10.21777/2500-2112-2018-4-50-59